The present invention generally relates to methods for fabricating integrated circuit and semiconductor devices and the resulting structures. More particularly, the present invention relates to metal-oxide-silicon (MOS) transistor devices for use in memory arrays, methods for making the same, and semiconductor devices containing the same.
One common device in integrated circuits (ICs) is a MOS transistor, such as those described in U.S. Pat. Nos. 5,658,811, 5,585,302, 5,668,394, 5,633,522, 5,567,647, 5,605,854, and 5,627,393, the disclosures of which are incorporated herein by reference. One type of MOS transistor, a MOS field-effect-transistor (MOSFET), can be characterized in one manner as either xe2x80x9cburied channelxe2x80x9d or xe2x80x9csurface channelxe2x80x9d depending on the location of the channel. In surface channel (SC) devices, the channel is located near the surface of the substrate where the gate oxide of the transistor is disposed, generally at a depth of about 100 xc3x85. In buried channel (BC) devices, the channel is located deeper in the substrate and further away from the gate oxide, generally at a depth of about 1000 xc3x85.
The performance of buried-channel and surface-channel MOSFET devices also differs. For example, the mobility of carriers (holes or electrons) in buried channels is about 15% higher than carriers in surface channels. Unfortunately, the advantages of BC MOSFETs are often outweighed by some of their disadvantages. As the size of MOSFET devices shrinks and gate lengths become smaller, the breakdown voltage (BVdSS) from the drain to the source, as well as control of the threshold voltage (Vt) in BC MOSFET devices become worse, as described in pages 294-303 of Silicon Processing For The VLSI Era by Wolf et al., the disclosure of which is incorporated herein by reference.
To better control BVdSS and Vt as device dimensions shrink, SC MOSFET devices have begun replacing BC MOSFET devices. SC MOSFET devices are easy to fabricate with salicide processes since the implanting step used to form the source and drain regions also implants the polysilicon gate. SC MOSFET devices, however, typically operate with a dual-gate operation that can require either a thick oxide layer during fabrication so p-dopants (such as boron) do not diffuse quickly into the surrounding areas and destroy the device performance or a hardened thin oxide layer where nitrogen is incorporated into the oxide layer. As device dimensions of SC MOSFET devices shrink into the submicron dimensions, these oxide layers unfortunately become too thin to prevent this out-diffusion of boron. Moreover, the fabrication processes for SC MOSFET devices often require additional masking steps during implantation of the channels, making manufacture more complex and costly.
The present invention provides methods for forming IC devices and the structures formed from these methods. Specifically, the present invention provides methods for forming IC devices containing SC MOS transistors. In particular, the present invention provides methods for fabricating SC MOSFET devicesxe2x80x94including both SC P-MOSFET and SC N-MOSFET devicesxe2x80x94without the additional masking steps that would conventionally be required during manufacture of SC MOSFET devices.
The methods of the present invention are practiced by the steps of providing a substrate with at least one isolation region and then forming a first dielectric layer over the substrate, and then forming a first polysilicon layer over the first dielectric layer. A portion of the first polysilicon layer is then removed to expose a portion of the first dielectric layer and at least one diffusion region is formed in the substrate underlying the exposed portion of the first dielectric layer. The exposed portion of the first dielectric layer is then removed, a second dielectric layer is then formed over the first polysilicon layer and the at least one diffusion region, and a second polysilicon layer is formed over the second dielectric layer. Next, the portions of the second dielectric layer and second polysilicon layer overlying the first polysilicon layer are removed, a conductive layer is deposited over the first and second polysilicon layers, and a third dielectric layer is formed over the conductive layer. Finally, an undesired portion of the third dielectric layer, conductive layer, first and second polysilicon layers, and first and second dielectric layers is removed. The first and second dielectric layers may comprise the same or different materials and/or may be the same or different thickness. The first and second polysilicon layers may be doped independently with different dopant species. The conductive layer may be tungsten silicide.
The present invention fabricates SC MOSFET devices without some of the masking steps that are conventionally required, thus lowering the cost for fabricating SC MOSFET devices. The present invention also provides flat polysilicon typography during fabrication of SC MOSFETS, allowing easier masking and etching of the polysilicon and easier fabrication of smaller device features. The present invention also fabricates a tungsten silicide strapped gate that is scalable to less than 0.25 micrometers with a low resist level.